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DTSTART;TZID=America/Denver:20231113T083000
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UID:submissions.supercomputing.org_SC23_sess244_tut129@linklings.com
SUMMARY:Node-Level Performance Engineering
DESCRIPTION:Georg Hager, Thomas Gruber, and Gerhard Wellein (FAU Erlangen-
 Nürnberg, Erlangen National High Performance Computing Center)\n\nThe gap 
 between peak performance and application performance is continuing to open
 . Paradoxically, bad node-level performance leads to highly scalable code,
  but at the price of increased overall time to solution. Consequently, val
 uable resources are wasted, often on a massive scale. If the user cares ab
 out time to solution on any scale, optimal performance on the node level i
 s often the key factor. We convey the architectural features of current pr
 ocessor chips, multiprocessor nodes, and accelerators, as far as they are 
 relevant for the practitioner. Peculiarities like SIMD vectorization, shar
 ed vs. separate caches, data transfer bottlenecks, and ccNUMA characterist
 ics are introduced, and the influence of system topology and affinity on t
 he performance of typical parallel programming constructs is demonstrated.
  Performance engineering and performance patterns are suggested as powerfu
 l tools that help the user understand the bottlenecks at hand and to asses
 s the impact of possible code optimizations. A cornerstone of these concep
 ts is the roofline model, which is described in detail, including useful c
 ase studies, limits of its applicability, and possible refinements. We als
 o show how simple performance tools can support node-level performance ana
 lysis by providing the developer with useful information about the bottlen
 ecks of their code.\n\nTag: Accelerators, Performance Optimization\n\nRegi
 stration Category: Tutorial Reg Pass\n\n
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