Contributor

Harald is an HPC system enthusiast with strong knowledge in monitoring systems, parallel programming models, compilers and computer architecture. He currently works at Intel Corp. on code modernization topics for the next generation HPC systems (including Xeon Phi and FPGA-based systems). Before that, he was the maintainer of the instrumentation library for the BSC performance tools suite (Extrae) while adapting it to new technologies and pursuing large scalability. In 2015, he received his Ph.D. in providing instantaneous metrics combining coarse-grain instrumentation and sampling techniques. His thesis resulted in a tool named Folding that easily points out the nature of the performance bottlenecks and their location in the application code. Not only this but during his research, he explored the performance of several in-production applications and applied simple and well-known code transformations to increase the application performance.